As the density of features to be created in an integrated circuit (IC) increases and the size of individual features decrease, such features are increasingly more difficult to accurately form with a photolithographic process. It is a well documented phenomenon in photolithographic processing that as a feature size becomes smaller than the wavelength of the light that is used to illuminate a mask or reticle pattern onto a wafer, the fringing effects of the illumination light produce errors on the wafer. Such errors distort the patterns created on a wafer in a manner that may decrease the performance of the resulting IC or cause it to fail completely.
To reduce or eliminate the illumination distortion, circuit designers use a variety of techniques including the use of optical and process correction (OPC) tools that, in effect, counteract the illumination distortions so that a feature will print as desired on the wafer. One example of an OPC correction tool is the Calibre® Software Suite, produced by Mentor Graphics Corporation of Wilsonville, Oreg., the assignee of the present invention.
Even when using an OPC tool, some features in an IC design may not print as desired on a wafer. In many instances, a less than desired OPC correction is made by the OPC tool due to manufacturing constraints that can affect the OPC tool in a non-intuitive manner. In these instances, users sometimes send test cases to the OPC software developers who debug the OPC software to determine why the less than optimal correction was made. A process of manual debugging takes time, increases the cost and decreases the throughput of overall circuit design process.
Given these problems, there is a need for a system that can alert a user when a less than desired OPC correction is being made and why a better correction is not possible under current system constraints.